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Semiconductor
July 1998
O OBS ESS E C PRO , SE WN, SIGNS RA E D 12 HD WIT O NEW 0, IR21 ART N 11 P 13 IR2 IR21
LET
E
HIP2500
Half Bridge 500VDC Driver
Features
* Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . 500V * Ability to Interface and Drive N-Channel Power Devices * Floating Bootstrap Power Supply for Upper Rail Drive * CMOS Schmitt-Triggered Inputs with Hysteresis and Pull-Down * Up to 400kHz Operation * Single Low Current Bias Supply * Latch-Up Immune CMOS Logic * Peak Drive. . . . . . . . . . . . . . . . . . . . . . . . . .Up to 2.0A * Gate Drive Rise Time (+125
oC) .
Description
The HIP2500 is a high voltage integrated circuit (HVIC) optimized to drive N-Channel MOS gated power devices in half bridge topologies. It provides the necessary control for PWM motor drive, power supply, and UPS applications. The SD pin allows external shutdown of gate drive to both upper and lower gate outputs. Undervoltage lockout will not allow gating when the bias voltage is too low to drive the external switches into saturation. The HIP2500IP is pin and function compatible to the International Rectifier IR2110. The HIP2500 has superior ability to accept negative voltages from the VS pin to the COM pin due to forward recovery of the lower flyback diode. The HIP2500IB is a SOIC or small outline IC form of the HIP2500. The HIP2500IB drives high side and low side referenced power switches just like the HIP2500IP. The HIP2500IP1 is a 16 lead Plastic DIP form of the HIP2500. Pins 4 and 5 removed from lead frame to provide extra creepage and strike distances in high voltage applications. Please see Application Note AN9010 for more information.
. . . . . . < 25ns (Typ)
Applications
* High Frequency Switch-Mode Power Supply * Induction Heating and Welding * Switch Mode Amplifiers * AC and DC Motor Drives * Electronic Lamp Ballasts * Battery Chargers * UPS Inverters * Noise Cancellation in Amplifier Systems
Functional Block Diagram
HIP2500 UV LEVEL SHIFT S LATCH R DRIVER HO VS VB
VDD HIN
Ordering Information
PART NUMBER HIP2500IP HIP2500IP1 HIP2500IB TEMP. RANGE (oC) -40 to +85 -40 to +85 -40 to +85 PACKAGE 14 Ld PDIP 16 Ld PDIP 16 Ld SOIC (W) PKG NO. E14.3 E16.3 M16.3
SD LOGIC LIN VSS UV DRIVER VCC LO COM
Pinouts
HIP2500 (PDIP) TOP VIEW
LO COM VCC NC VS VB HO 1 2 3 4 5 6 7 14 NC 13 VSS 12 LIN 11 SD 10 HIN 9 8 VDD NC LO COM VCC NC NC VS VB HO 1 2 3 4 5 6 7 8
HIP2500 (SOIC) TOP VIEW
16 15 14 13 12 11 10 9 NC VSS LIN SD HIN VDD NC NC VS VB HO 6 7 8 LO COM VCC 1 2 3
HIP2500 (PDIP) TOP VIEW
16 15 14 13 12 11 10 9 NC VSS LIN SD HIN VDD NC NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright
(c) Harris Corporation 1997
File Number
2801.9
1
HIP2500
Absolute Maximum Ratings
Full Temperature Range Unless Otherwise Noted, All Voltages Referenced to VSS Unless Otherwise Noted.
Thermal Information
Thermal Resistance (Note 1, Typical) JA HIP2500IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W HIP2500IP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W HIP2500IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90oC/W See Maximum Power Dissipation vs Temperature Curve Junction Temperature Range . . . . . . . . . . . . . . . . . -40oC to +125oC Storage Temperature Range, TS . . . . . . . . . . . . . . . -40oC to +150oC Operating Ambient Temperature Range, TA . . . . . . . -40oC to +85oC
Floating Supply Voltage, VB . . . . . . . . . . . . . . .VS-0.5V to VS+18.0V (Positive Terminal) Floating Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V (Common Terminal) High Side Channel Output Voltage, VHO . . . . . . . . -0.5V to VB+0.5V Fixed Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.5V to 18.0V Low Side Channel Output Voltage, VLO . . . . . . . .-0.5V to VCC+0.5V Logic Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . -0.5V to 18.0V Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V [HIN, LIN & SD (Shutdown)] VDD to COM and VCC to VSS Voltage . . . . . . . . . . . . . -0.5V to 18.0V NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended DC Operating Conditions
Floating Supply Voltage, VB . . . . . . . . . . . . . . . . VS+10V to VS+15V (Floating Terminal) High Side Channel Output Voltage, VHO . . . . . . . . . . . . . .10V to VB (With Respect to VS) Fixed Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .10V to 15V Low Side Channel Output Voltage, VLO . . . . . . . . . . . . . . 0V to VCC Logic Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . 4V to VCC Floating Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . -4.0V to 500V (Common Terminal) VSS and COM potentials to be equal.
Electrical Specifications
VCC = (VB - VS) = VDD = 15V, COM = VSS = 0, Unless Otherwise Noted TJ = +25oC TJ = -40oC TO +125oC MAX MIN TYP MAX UNITS
PARAMETER DC CHARACTERISTICS Quiescent VCC Current Quiescent VBS Current Quiescent VDD Current Quiescent Leakage Current Logic Input Pulldown Current, VIN = VDD (HIN, LIN, SD) Logic Input Leakage Current, VIN = VSS (HIN, LIN, SD) Logic Input Positive Going Threshold (Note 2) Logic Input Negative Going Threshold (Note 2) Undervoltage Positive Going Threshold Undervoltage Negative Going Threshold Undervoltage Hysteresis (VCC) Undervoltage Hysteresis (VBS) Output High Open Circuit Voltage (HO, LO) Output Low Open Circuit Voltage (HO, LO) Output High Short Circuit Current (Sourcing) Output Low Short Circuit Current (Sinking) NOTE:
SYMBOL
MIN
TYP
IQCC IQBS IQDD IS (500V) IN+
-
1.5 300 0.1 0.4 12
1.9 400 1 3.0 20
-
300 -
2.0 435 1.8 22
mA A A A A A V V V V mV mV V V A A
IN-
-
0
1
-
0
1
VTH+ VTHUV+ UVUVHYS (VCC) UVHYS (VBS) VOUT + VOUT IOUT + IOUT -
7.5 5.5 8.0 7.7 250 250 14.95 1.65 1.85
8.0 5.9 9.35 9.05 15 2.1 2.3
8.5 6.3 9.99 9.69 450 450 0.05 -
7.5 5.5 7.8 7.5 170 170 14.95 1.15 1.35
8.0 5.9 15 1.6 1.7
8.6 6.4 9.99 9.69 530 530 0.05 -
2. See Figure 8 for logic supply voltages other than 15.0V.
2
HIP2500
Switching Specifications
TJ = +25oC PARAMETER SYMBOL MIN TYP MAX TJ = -40oC TO +125oC MIN TYP MAX UNITS
HIGH SIDE CHANNEL WITH 500V OFFSET, CL = 1000pF High Side Turn-On Propagation Delay High Side Turn-Off Propagation Delay High Side Rise Time High Side Turn-Off Fall Time LOW SIDE CHANNEL, CL = 1000pF Low Side Turn-On Propagation Delay Low Side Turn-Off Propagation Delay Low Side Turn-On Rise Time Low Side Turn-Off Fall Time Shutdown Propagation Delay High Side Shutdown Low Side Shutdown tSDHO tSDLO 300 175 400 320 490 400 200 125 650 500 ns ns tON tOFF tR tF 250 175 365 295 25 25 450 370 50 50 190 125 30 30 600 475 50 50 ns ns ns ns tON tOFF tR tF 320 260 420 385 25 25 525 450 50 50 230 190 25 25 725 625 50 50 ns ns ns ns
HIGH SIDE CHANNEL WITH 500V OFFSET, CL = 1000pF Turn-On Propagation Delay Matching (Between HO and LO) Minimum On Output Pulse Width (HO, LO) Minimum Off Output Pulse Width (HO, LO) Minimum On Input Pulse Width (HIN, LIN) Minimum Off Input Pulse Width (HIN, LIN) Deadtime LO Turn-Off to HO Turn-On Deadtime HO Turn-Off to LO Turn-On MAXIMUM TRANSIENT CONDITIONS Offset Supply Operating Transient dVS/dt 50 50 V/ns Mt PWOUT(MIN) PW OUTMIN PWON(MIN) PWOFF(MIN) DHtON DLtON 0 125 0 185 ns
275 -
35 440 100 110 125 -20
50 640 145 200 -
250 -
35 440 100 110 125 -20
55 650 175 220 -
ns ns ns ns ns ns
Logic Truth Table
HIN 0 0 1 1 X X X 1 LIN 0 1 0 1 X X 1 X UVH 0 0 0 0 X 1 1 0 UVL 0 0 0 0 X 1 0 1 SD 0 0 0 0 1 X 0 0 HO 0 0 1 1 0 0 0 1 LO 0 1 0 1 0 0 1 0 Normal Off Lower On Upper On Both On Chip Disabled VCC UV Lockout and VBS Lockout VBS UV Lockout VCC UV Lockout COMMENTS
3
HIP2500 Typical Performance Curves
2.5 MAXIMUM POWER DISSIPATION (W) 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120130 AMBIENT TEMPERATURE ( C)
o
HIGH VOLTAGE POWER DISSIPATION (W)
1.0 VBIAS = 15V CL = 100pF TA = +25oC 0.1 VS = 400V VS = 300V VS = 200V VS = 100V
HIP2500-IP HIP2500-IP1 HIP2500-IB
0.01
0.001 10
100 SWITCHING FREQUENCY (kHz)
1000
FIGURE 1. MAXIMUM POWER DISSIPATION vs TEMPERATURE
FIGURE 2. HIGH VOLTAGE POWER DISSIPATION vs SWITCHING FREQUENCY
10 VS = VSS = COM VBS = VCC = 15VDC TA = +25oC 1.0 LOGIC SUPPLY OFFSET VOLTAGE (V)
6 MAX VSS OFFSET 4
POWER DISSIPATION (W)
2
2100pF 0.1 907pF 100pF
0
-2 MIN VSS OFFSET
0.01 10
100 SWITCHING FREQUENCY (kHz)
1000
-4 10 12 14 16 SUPPLY VOLTAGE (V)
NOTE: All switching losses assumed to be in IC. FIGURE 3. LOW VOLTAGE POWER DISSIPATION vs FREQUENCY FIGURE 4. VSS OFFSET vs VCC SUPPLY VOLTAGE
MAX VS OFFSET VOLTAGE (NEGATIVE)
10 OFFSET SUPPLY LEAKAGE CURRENT (A) 200V 500V 400V 300V 1.0 100V
10 9 8 7 6 5 4 3 2 10 11 12 13 14 15 16 BOOTSTRAP SUPPLY VOLTAGE 17 18 VCC = 15V VCC = 12V VCC = 15V AND 12V TJ = +25oC
0.1 0 20 40 60 80 100 TEMPERATURE (oC) 120 140
FIGURE 5. OFFSET SUPPLY LEAKAGE vs TEMPERATURE
FIGURE 6. MAXIMUM NEGATIVE VS OFFSET VOLTAGE vs VBS VOLTAGE
4
HIP2500 Typical Performance Curves
9.35 UNDERVOLTAGE LOCKOUT (V) 9.3 9.25 9.2 9.15 9.1 9.05 9.0 8.95 8.9 -40 -20 0 20 60 80 40 TEMPERATURE (oC) VBS UVVBS UV+ VCC UVLOGIC THRESHOLD (V) VCC UV+ 8 VTH+ 6
(Continued)
10 TJ = -40oC TO +125oC
VTH4
2 100 120 140 5 6 8 10 12 14 16 18 LOGIC SUPPLY VOLTAGE (V) (VDD TO VSS)
FIGURE 7. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
FIGURE 8. INPUT LOGIC THRESHOLD vs SUPPLY VOLTS
450 RISE AND FALL TIMES (ns) VBS SUPPLY CURRENT (A) 400 350 300 250 200 150 -50 14V IQBS1 14V IQBS0 18V IQBS1 18V IQBS0
120 100 80 60 40 20 tF 0 50 100 JUNCTION TEMPERATURE (oC) 150 0 100 1000 LOAD CAPACITANCE (pF) 1E4
10V IQBS1 10V IQBS0
tR
FIGURE 9. QUIESCENT VBS SUPPLY CURRENT vs TEMPERATURE
FIGURE 10. RISE AND FALL TIME vs LOAD CAPACITANCE
3.0 PEAK OUTPUT CURRENT (A) RISE AND FALL TIME (ns) 2.5 2.0 1.5 1.0 0 0.5 0 0 2 4 6 8 10 12 14 SOURCE/SINK DRAIN-SOURCE VOLTAGE 16 25 125 SOURCE DRIVER SINK DRIVER -40 -40 0 25 125
30 28 26 24 22 20 18 16 14 12 10 -50 0 50 TEMPERATURE (oC) 100 150 tR tF
FIGURE 11. DRIVER SINK/SOURCE V-I CHARACTERISTIC
FIGURE 12. RISE AND FALL TIME vs TEMPERATURE
5
HIP2500 Typical Performance Curves
30 28 26 24 22 20 18 16 14 12 10 10 11 12 13 14 15 16 tR tF PROPAGATION DELAY (ns) RISE AND FALL TIME (ns)
(Continued)
460 440 420 400 380 360 340 320 300 10 11 LtOFF 12 13 14 SUPPLY VOLTAGE (V) 15 16 LtON HtOFF HtON
SUPPLY VOLTAGE (V)
FIGURE 13. RISE AND FALL TIME vs SUPPLY VOLTAGE
FIGURE 14. PROPAGATION DELAY vs SUPPLY VOLTAGE
700 PROPAGATION DELAY (ns) HtON HtOFF 500 LtON LtOFF
600
400
300
200 -50
0 50 100 JUNCTION TEMPERATURE (oC)
150
FIGURE 15. PROPAGATION DELAYS AT VCC = 15V
Typical Application Diagram
HV HIP2500 UV LEVEL SHIFT S LATCH R HIN CF SD LOGIC LO LIN UV DRIVER COM VSS RG DF TO LOAD VCC DRIVER VB HO VS RG
VDD
VCC
6
HIP2500 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14
2.93
7
HIP2500 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 16
2.93
8
HIP2500 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 10.10 7.40 MAX 2.65 0.30 0.51 0.32 10.50 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.3977 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.4133 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 16 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 16 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
9

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